Atari 2600 / F247
BEING VERIFIEDIMPLIED TRANSFERS AND REGISTER STEPS JOIN THE ORDERED BUS
- STATUS
- BEING VERIFIED
- AREA
- Timing / bus
- RECORDED
- 2026-07-16
- PUBLIC SOURCE
- Research dossier / finding 247
- RECORD ID
atari2600-f247- SNAPSHOT
f114355884d03a2c
HYPOTHESIS: the MOS section 5.3 implied-addressing sequence is not unique to status controls. TAX, TAY, TXA, TYA, TSX, TXS, INX, INY, DEX, and DEY must also fetch their opcode at PC, read the incremented PC address during cycle two, and only then expose their architectural register/flag mutation.
Raw traces, ROM material, local paths, and personal data are not part of this public record.
01INPUT IDhash receipt
02BYTE MAPdecode coverage
03CPU STATEtrace comparison
04BUS / TIMEordered effects
05OUTPUTvisual · audio · input
06ARTIFACTbuild identity