RIOT TIMER FIRST-COUNT PHASE AND INTERRUPT FLAGS

The runtime previously loaded the full selected divider into its prescaler on every TIM1T/TIM8T/TIM64T/T1024T write. That delayed underflow until (N + 1) interval, even though the Rockwell R6532 data sheet starts the first decrement one CPU cycle after the write and underflows at N interval + 1.

Raw traces, ROM material, local paths, and personal data are not part of this public record.