1998 / SYSTEM 14
Sega Dreamcast
RESEARCH AVAILABLERESEARCHRESEARCH PUBLISHED
PRODUCTION FINDINGSNOT STARTED
PUBLIC SOURCE DOCUMENTOPEN THE PUBLIC RESEARCH DOSSIER →
01
SYSTEM MODEL
HARDWARE AT A GLANCE
A navigable map of the public dossier. It shows documented hardware domains, not physical wiring or implementation status.
PUBLIC DOSSIER MAPSega DreamcastEXTERIOR REFERENCE + DOCUMENTED HARDWARE DOMAINS
01SH-4 CPU: instruction set, registers, and pipeline02PowerVR CLX2 (Holly): tile-based deferred rendering03Yamaha AICA: 64-channel sound with ARM7DI core04Memory architecture and address map05GD-ROM: proprietary disc format and controller06Maple bus: controller protocol and peripherals07Conclusion08I/O Dispatch Reference (Final Synthesis)09I/O Dispatch Deepening (Maximum Depth Synthesis)
02
RESEARCH GUIDE
DOCUMENTED HARDWARE
Research chapters explain the hardware. Production records separately show what REFORGE has tested or corrected.
01SH-4 CPU: instruction set, registers, and pipeline8 SUBTOPICS
02PowerVR CLX2 (Holly): tile-based deferred rendering6 SUBTOPICS
03Yamaha AICA: 64-channel sound with ARM7DI core5 SUBTOPICS
04Memory architecture and address map3 SUBTOPICS
05GD-ROM: proprietary disc format and controller2 SUBTOPICS
06Maple bus: controller protocol and peripherals7 SUBTOPICS
07ConclusionCHAPTER OVERVIEW
08I/O Dispatch Reference (Final Synthesis)9 SUBTOPICS
READ CHAPTER
- AICA Audio Registers (G2-bus, $00700000 base)
- GD-ROM Controller Registers (G1-bus, $A05F7000 base)
- Maple Bus DMA Registers ($A05F6C00 base)
- SH-4 DMAC + Store Queue
- PVR Tile Accelerator (TA) Parameter Format
- Additional Holly Registers ($A05F8000+)
- Complete I/O Register Dispatch Table
- Integration with Existing Pipeline
- Verification Notes
09I/O Dispatch Deepening (Maximum Depth Synthesis)9 SUBTOPICS
READ CHAPTER
- AICA DSP — ARM7 Address Space + Upload Protocol
- GD-ROM — Full ATAPI Command Table + ASC/ASCQ Error Codes
- Maple Bus — Wire Protocol Timing + Response Parsing
- SH-4 DMAC — Channel Control Bits + DMA Contention Matrix
- PVR TA — Named Registers + Dual FIFO
- Holly/PVR Video Output — Timing Tables + Quad-Buffer Swap
- Expanded I/O Register Dispatch Table
- Cross-Subsystem DMA Coordination
- Additional Verification Notes (Maximum Depth)
03
VERIFICATION
PARITY BOUNDARIES
A passed boundary applies only to the named claim and evidence row below.
01INPUT IDhash receipt
02BYTE MAPdecode coverage
03CPU STATEtrace comparison
04BUS / TIMEordered effects
05OUTPUTvisual · audio · input
06ARTIFACTbuild identity
L0BUILDS
A native artifact is produced.
L1LIVES
The requested headless run completes.
L2RENDERS
Fresh visible output is verified.
L3RESPONDS
Scripted input changes title state.
L4MECHANICS
Named game rules pass deterministic checks.
L5ACCEPTED
Corpus, build receipt, and human acceptance gates pass.
| SYSTEM / PUBLIC RESULT | L0BUILDS | L1LIVES | L2RENDERS | L3RESPONDS | L4MECHANICS | L5ACCEPTED |
|---|---|---|---|---|---|---|
| Sega DreamcastHardware dossier published; native-runtime verification not started | NOT TESTED | NOT TESTED | NOT TESTED | NOT TESTED | NOT TESTED | NOT TESTED |
04
PUBLIC SOURCES
READ THE DOCUMENTS
The public dossier is the readable source document. External references are linked separately so their scope can be checked directly.
Public research dossierThe readable publication of the working research document. Local paths, raw traces, and personal data are removed.OPEN PUBLIC DOCUMENT →Dreamcast hardware overviewSH-4, PowerVR2, AICA, memory, storage, and network overviewdreamcast.wiki ↗Dreamcast development referenceHardware reference, graphics, audio, Maple, VMU, and optimization linkswww.dreamcast.wiki ↗
05
PRODUCTION LEDGER
FINDINGS
PRODUCTION VERIFICATION NOT STARTEDThis page currently documents hardware research. No implementation result is recorded for this system yet.