1985 / SYSTEM 06
Sega Master System
RESEARCH AVAILABLESYSTEM MODEL
HARDWARE AT A GLANCE
A navigable map of the public dossier. It shows documented hardware domains, not physical wiring or implementation status.
RESEARCH GUIDE
DOCUMENTED HARDWARE
Research chapters explain the hardware. Production records separately show what REFORGE has tested or corrected.
011. CPU architecture — Z80 at 3.579545 MHz6 SUBTOPICS
022. VDP — Sega 315-5124 (Mode 4, sprites, scrolling, line interrupt)10 SUBTOPICS
033. Memory map — complete address space and I/O ports4 SUBTOPICS
044. Audio — SN76489 PSG + YM2413 OPLL3 SUBTOPICS
055. Bank switching — Sega, Codemasters, and Korean mappers4 SUBTOPICS
066. I/O and controllers — D-pad, buttons, Pause NMI, Light Phaser4 SUBTOPICS
077. Recompilation notes — critical quirks for REFORGE10 SUBTOPICS
- VDP command word timing
- Sprite overflow flag and collision
- Line interrupt internal counter
- Vertical scroll wrap at 224
- VDP data port read-ahead buffer
- The first 1 KB protection and recompilation implications
- EI delay and interrupt acceptance
- VDP status register read side effects
- Scanline-accurate VDP rendering
- Bank switch detection in recompiled code
VERIFICATION
PARITY BOUNDARIES
A passed boundary applies only to the named claim and evidence row below.
A native artifact is produced.
The requested headless run completes.
Fresh visible output is verified.
Scripted input changes title state.
Named game rules pass deterministic checks.
Corpus, build receipt, and human acceptance gates pass.
| SYSTEM / PUBLIC RESULT | L0BUILDS | L1LIVES | L2RENDERS | L3RESPONDS | L4MECHANICS | L5ACCEPTED |
|---|---|---|---|---|---|---|
| Sega Master SystemHardware dossier published; native-runtime verification not started | NOT TESTED | NOT TESTED | NOT TESTED | NOT TESTED | NOT TESTED | NOT TESTED |
PUBLIC SOURCES
READ THE DOCUMENTS
The public dossier is the readable source document. External references are linked separately so their scope can be checked directly.
PRODUCTION LEDGER