Timer and STAT timing must be observable before visual rebaseline

The first timing iteration keeps the existing logical scanline boundary but adds a 456-T-cycle accumulator for the SM83 divider. TAC-selected timer edges, the four-T-cycle TIMA reload delay, DIV reset behavior, and STAT rising-edge requests are now emitted in the Game Boy I/O runtime.

Raw traces, ROM material, local paths, and personal data are not part of this public record.