REFORGE

1989 / SYSTEM 07

Game Boy / Game Boy Color

CURRENTLY BEING WORKED ON
Game Boy / Game Boy Color exterior blueprintA console-specific exterior profile for Game Boy / Game Boy Color, repeated in the system model when a hardware architecture is available.PROFILE / 1989FRONT REFERENCE
EXTERIOR BLUEPRINT CONSOLE-SPECIFIC PROFILE · SHARED WITH SYSTEM MODEL
RESEARCHRESEARCH PUBLISHED
PRODUCTION FINDINGS26 RECORDED
PUBLIC SOURCE DOCUMENTOPEN THE PUBLIC RESEARCH DOSSIER →
CPUSharp SM83
CLOCK4.194304 MHz
WRAM8 KiB DMG / 32 KiB CGB
DISPLAY160 × 144
AUDIO4 channels
INPUT8-button matrix
01

SYSTEM MODEL

HOW THE HARDWARE INTERLOCKS

A functional relationship model. Connections are logical and do not replace chip-level schematics.

HARDWARE ARCHITECTURE FUNCTIONAL MAP · CONNECTIONS ARE LOGICAL
Game Boy and Game Boy Color hardware architectureA functional board map connects cartridge memory-bank control to the SM83 processor and system bus, then to memory, graphics, audio, timing, serial, and joypad hardware. The exterior reference repeats the same handheld shown above.CARTRIDGE + MBCROM · RAM · RTCSM83 CPU16-BIT ADDRESS BUSSYSTEM BUSDMG / CGB ROUTINGADDRESS · DATA · INTERRUPTSWRAM / HRAMECHO · STACKPPUVRAM · OAM · PALETTESAPU4 AUDIO CHANNELSTIMER / IRQDIV · TIMA · IFJOYPADACTIVE-LOW MATRIXSERIAL / LINKSB · SCDMG HANDHELDSHARED EXTERIOR REFERENCELCD VIEWPORTD-PAD · A/B · START/SELECT
02

RESEARCH GUIDE

DOCUMENTED HARDWARE

Research chapters explain the hardware. Production records separately show what REFORGE has tested or corrected.

PUBLIC DOSSIER11 CHAPTERS · 48 SUBTOPICSOpen a chapter for its subtopics, or continue into the full dossier.
01CPU — Sharp LR35902 (SM83)5 SUBTOPICS
READ CHAPTER
02PPU (Pixel Processing Unit)10 SUBTOPICS
READ CHAPTER
03GBC enhancements6 SUBTOPICS
READ CHAPTER
04Complete memory map1 SUBTOPIC
READ CHAPTER
05Memory Bank Controllers6 SUBTOPICS
READ CHAPTER
06Audio — DMG APU8 SUBTOPICS
READ CHAPTER
07Timer system3 SUBTOPICS
READ CHAPTER
08Joypad ($FF00)CHAPTER OVERVIEW
READ CHAPTER
09Boot ROM and initial register state2 SUBTOPICS
READ CHAPTER
10Hardware errata and recompilation edge cases7 SUBTOPICS
READ CHAPTER
11ConclusionCHAPTER OVERVIEW
READ CHAPTER
03

VERIFICATION

PARITY BOUNDARIES

A passed boundary applies only to the named claim and evidence row below.

PUBLIC RESULT UNTESTED BOUNDARIES REMAIN VISIBLE
L0BUILDS

A native artifact is produced.

L1LIVES

The requested headless run completes.

L2RENDERS

Fresh visible output is verified.

L3RESPONDS

Scripted input changes title state.

L4MECHANICS

Named game rules pass deterministic checks.

L5ACCEPTED

Corpus, build receipt, and human acceptance gates pass.

SYSTEM / PUBLIC RESULTL0BUILDSL1LIVESL2RENDERSL3RESPONDSL4MECHANICSL5ACCEPTED
Game Boy / Game Boy ColorNative build and 1,800-frame liveness recorded; title-level verification not claimedPASSEDPASSEDNOT TESTEDNOT TESTEDNOT TESTEDNOT TESTED
04

PUBLIC SOURCES

READ THE DOCUMENTS

The public dossier is the readable source document. External references are linked separately so their scope can be checked directly.

Public research dossierThe readable publication of the working research document. Local paths, raw traces, and personal data are removed.OPEN PUBLIC DOCUMENT →Pan DocsPublic Game Boy hardware referencegbdev.io ↗Memory mapDMG/CGB address spaces and mapped hardwaregbdev.io ↗RenderingPPU modes, timing, and access boundariesgbdev.io ↗GraphicsTiles, maps, sprites, and LCD outputgbdev.io ↗CGB registersColor hardware, banks, palettes, and speed stategbdev.io ↗Cartridge headerEntry point, mapper identity, sizes, and checksumsgbdev.io ↗
05

PRODUCTION LEDGER

FINDINGS