Atari Pong / Home Pong

The original Atari Home Pong (model C-100, sold by Sears as Tele-Games Pong for Christmas 1975 at $98.95) used Atari's proprietary chip 3659-1C. Approximately 150,000 units were built for the Sears launch, with ~50,000 additional Atari-branded units in 1976. The chip implemented a single game (Pong) for two players with digital on-screen scoring and a distinctive rainbow color effect achieved by deliberately offsetting the crystal oscillator to 3.679 MHz (vs. the standard 3.579 MHz NTSC colorburst), causing continuous color phase drift.

Both chips share the same fundamental approachLFSR-based timing counters generate the video raster, combinational logic renders game elements by comparing scan position against stored object positions, and all "physics" reduce to direction-flip registers triggered by boundary comparisons.

The AY-3-8500-1 (NTSC version) is a 28-pin DIP with four separate video outputs, a dedicated sync output, analog paddle inputs, digital game-select inputs, and a master clock input. The -1 suffix designates NTSC (525-line); the unsuffixed AY-3-8500 is PAL (625-line).

Absolute maximum ratings: Voltage on any pin −0.3V to +12V vs. Vss; operating temperature 0–40°C; storage −20–70°C. Logic output low ≤ 1.0V at 0.5 mA sink; logic output high ≥ Vcc − 2V at 0.1 mA source. Game selection is one-hot (ground one pin at a time). When no game pin is grounded, an undocumented 7th game ("Handicap" — Soccer with an extra defensive paddle for the right player) activates.

The chip contains no instruction sequencer. Instead, all behavior emerges from twelve hardwired functional blocks, each built from NOR gates (the fundamental NMOS building block), SR latches, and LFSR counters.

Clock circuitry takes the external 2.012 MHz signal and generates two alternating internal clock phases at ~1.006 MHz via a capacitor-latch divider. A "linger" node — a transistor gate with no pullup — exploits gate capacitance to hold charge briefly, creating a non-overlapping two-phase clock. This is the heartbeat for all downstream logic.

Horizontal countera 7-bit LFSR with XNOR feedback from bits 0 and 6. It cycles through 128 states per scanline (128 × 500 ns = 64 µs per line). A 14-output binary decoder fires control signals at specific LFSR states, marking screen landmarks: left wall at 11 µs, center line at 31 µs, right wall at 49 µs, H-sync start at 60 µs, and H-sync end/counter reset at 64 µs.

Vertical counteran 8-bit LFSR with XNOR feedback from bits 4 and 7, advanced once per horizontal line via a divide-by-2 circuit off the horizontal reset signal. The NTSC version cycles through 262 states per field. A 10-output decoder marks vertical landmarks: top border at line 84, score region lines 88–136, goal walls at lines 164–384, bottom border at line 464, V-sync start at line 516, and V-sync end/counter reset at line 524.

Score display consumes approximately one-eighth of the die area — the largest identifiable subsystem. Scores (0–15 per player) are stored in 4-bit counters. The digit shapes are not stored in ROM; they are generated by hardwired binary pattern testing — combinational logic that tests the current 4-bit score value against the current row/column position within the digit area, functioning as an embedded truth table. Each digit is roughly 5 pixels wide × 20 scanlines tall (NTSC). Player 1's score displays at horizontal position 24–29 µs; Player 2's at 33–38 µs.

The AY-3-8500 generates a non-interlaced progressive-scan signal despite the "525-line" NTSC designation. Here are the exact timing specifications:

Horizontal sync generation uses an SR latchhorizontal control signal #13 (at 60 µs) sets the latch, grounding the sync output pin; signal #14 (at 64 µs) resets it and simultaneously resets the horizontal LFSR counter. The result is a clean 4 µs sync pulse repeating every 64 µs. Vertical sync works identically: vertical control signal #1 (at line ~258) sets the V-sync latch; signal #2 (at line ~262) resets it and the vertical counter, producing a ~256 µs sync pulse.

The chip produces four separate digital video outputs (ball, left paddle, right paddle, field/score) plus the sync output. These are combined externally through a resistor summing network: sync through a 510Ω resistor, a 220Ω pull-down to ground, and each video output through resistors of varying values to set grayscale levels. The resulting composite signal has 0V sync tips, ~0.3V black level, and ~0.7–1.0V white level. Different resistor values per output allow subtle luminance differences between game elements.

The composite baseband signal feeds an RF modulator (typically ASTEC or Mitsumi), a self-contained shielded metal-can module that amplitude-modulates the video onto a VHF carrier at Channel 3 (~61.25 MHz) or Channel 4 (~67.25 MHz). Output connects to the TV's antenna terminals via a TV/Game switchbox.

The divider chain summary2.012 MHz → ÷2 (internal clock ~1.006 MHz) → ÷128 (7-bit LFSR → H-sync ~15,720 Hz) → ÷262 (8-bit LFSR → V-sync ~59.6 Hz). Total division ratio: ×33,536 from master clock to field rate.

Both the Atari custom chip and the AY-3-8500 use the same fundamental technique: a potentiometer charges a capacitor, and the time to reach a comparator threshold encodes the paddle's vertical screen position.

• Supply voltage: 6–9V (six 1.5V cells or external adapter)
• Logic levels: Output low ≤ 1.0V; output high ≥ Vcc − 2V
• Controller type on C-100: Built-in paddle knobs — potentiometers mounted directly on the PCB, with rotary knobs protruding through the console housing
• No standard connector on the C-100 (controllers hardwired). Detachable controllers first appeared on the Sears Super Pong. The DB9 (DE-9) connector standard arrived only with the Atari 2600 in 1977
• Controller jacks on Ultra Pong Doubles: 2.5 mm mono headphone jacks for four detachable paddles

Atari produced eight distinct dedicated console models between 1975 and 1977, each using proprietary custom chips — never the GI AY-3-8500. All featured built-in speakers (sound was not sent to the TV) and the rainbow color effect via the offset 3.679 MHz crystal.

The C-100 → C-140 progression added a game-select switch and three additional game modes (Super Pong, Catch, Practice/Solitaire) while keeping the identical form factor. The C-200 Pro-Am introduced difficulty modes (Professional: faster ball, smaller paddles, steeper angles; Amateur: the opposite) and the first computer-controlled opponent for single-player mode. The C-402 Ultra Pong dramatically expanded to 16 base games across four categories — Pong, Hockey, Barrier Pong, Barrier Hockey — each in Regular, Super, Hyper, and Ultra speed variants, for 32 total game variations.

Video Pinball (C-380) was the most technically advanced, using a microcontroller with RAM rather than pure hardwired logic — representing Atari's transition toward programmable hardware. Stunt Cycle (C-450) was the only Atari-branded console to use a GI chip (AY-3-8760-1). Interestingly, the Sears version bundled both the AY-3-8760 and Atari's C010765 chip for 16 additional Pong games.

The GI AY-3-85xx chip family evolved in parallel for the clone market: AY-3-8500 (1976, 6 games, B&W) → AY-3-8550 (1976, pin-compatible, adds horizontal paddle motion) → AY-3-8600/8610 (1977, 8–10 games, new pinout, 3.58 MHz clock) → AY-3-8510/8512 (1978, compact 16-pin DIP, built-in color). Companion color chips included the AY-3-8515 (for 8500-series) and AY-3-8615 (for 8600-series).

Because there is no instruction stream to decode, "emulation" of Pong hardware means one of three things: transistor-level simulation, gate/RTL-level FPGA synthesis, or functional behavioral modeling. All three have been accomplished.

Transistor-level simulation was achieved by Cole Johnson in 2018, building on Sean Riddle's 2017 acid-decap die photographs. Johnson manually traced every metal connection and transistor from microscope images, producing a complete netlist. His JavaScript simulator (inspired by the Visual 6502 project) represents each of the 3,213 transistors as a switch, modeling NMOS pullup/pulldown behavior. It is accurate to individual clock cycles but far too slow for real-time play — useful only for debugging and understanding circuit behavior.

Compiled software simulation uses the pipelinetransistor netlist → DLAET → Verilog → Verilator → optimized C++. Verilator compiles the Verilog description into C++ that runs roughly 100× faster than interpreted simulation (iVerilog). Johnson estimated that 75% of AY-3-8500 clock cycles are spent simply incrementing the two LFSR counters, offering significant optimization potential. Integration with MAME has been discussed — MAME already has a netlist subsystem (by "couriersud") that handles discrete-logic arcade games at the TTL chip level, successfully emulating the original arcade Pong, Breakout, and Rebound.

For the original arcade Pong's discrete TTL circuit (66 chips + 555 timers), Stephen Edwards published a comprehensive reconstruction paper in 2012 ("Reconstructing Pong on an FPGA," Columbia University), and Paul Falstad built an interactive JavaScript circuit-level simulation at falstad.com/pong/ that models each TTL chip individually.