Nintendo 64

NEC VR4300 (MIPS R4300i derivative) @ 93.75 MHz (RCP @ 62.5 MHz). Full MIPS III ISA (superset of MIPS I).

MIPS III additions over MIPS I

64-bit GPRs (32×64-bit, R0=0) and opsDADD/DADDU/DADDI/DADDIU/DSUB/DSUBU/DMULT/DMULTU/DDIV/DDIVU, 64-bit shifts (DSLL/DSLL32/DSLLV/DSRA/DSRA32/DSRAV/DSRL/DSRL32/DSRLV), 64-bit loads/stores (LD/SD/LDL/LDR/SDL/SDR/LLD/SCD), DMFC1/DMTC1.

Atomic LL/SC, trap instructions (TGE/TGEU/TLT/TLTU/TEQ/TNE), expanded SYSCALL/BREAK.

Games run almost exclusively in 32-bit mode (KSEG0/KSEG1 direct mapping); 64-bit ops are rare but must be emulated exactly. 5-stage pipeline: IC → RF → EX → DC → WB. Single-issue in-order. Branch delay slot = 1 instruction. Load interlock handled in hardware. FPU (COP1): IEEE-754 single/double. 32×32-bit FPRs (or 16×64-bit). ADD.S/MUL.D/CVT.S.W/BC1T/BC1F + FCR0/FCR31.

TLB32 double-entries (64 pages). PageMask (CP0 reg 5) = 0 (4 KB default on N64). EntryHi (VPN2+ASID), EntryLo0/Lo1 (PFN + C/D/V/G). Operations: TLBWI/TLBWR/TLBP/TLBR. Rare usage: only Mario 64 intro probe + a few Rare/homebrew titles. Commercial games use KSEG0 (cached, subtract 0x80000000) or KSEG1 (uncached, subtract 0xA0000000).

Caches16 KB I-cache (direct-mapped, 8-byte line, virtually indexed/physically tagged). 8 KB D-cache (direct-mapped, write-back, 8-byte line).

CP0 Exception Vectors (BEV=0 normal post-boot)

TLB Refill0x80000000 General Exception (incl. MI/RCP interrupts): 0x80000180 Bootstrap (IPL3): 0xBFC00200 / 0xBFC00380

Full MI/PI/RI Register Bitfields & Clearing

MI_INTR (0x04300008)bits 5:0 = DP/PI/VI/AI/SI/SP (read-only). MI_INTR_MASK (0x0430000C): set/clear pairs. PI_STATUS (0x04600010): write 1 to bit 1 clears IRQ. RI_ERROR (0x04700018): write any value clears. Clearing pseudocode: mi_clear_vi() = write VI_V_CURRENT; mi_clear_dp() = MI_MODE |= (1<<11); pi_clear_irq() = PI_STATUS |= (1<<1).

Separate MIPS-like VU @ 62.5 MHz. 4 KB IMEM + 4 KB DMEM. DMA-loaded microcode. Vector Registers: 32×128-bit (8×16-bit signed lanes, big-endian).

COP2 Format (32-bit)

31-26COP2 | 25-21: opcode | 20-16: vs | 15-11: vd | 10-6: vt | 5-0: element

Full Load/Store Encodings (LWC2 family)

LQV/LRV/LTV/STV etc. with byte-lane pseudocode (see Iter 3 for exact wrapping/transpose). Accumulator: 48-bit per lane, clamp on extract.

Audio ABI Commands (8-byte, opcode first byte; full 16-command table in Iter 4).

Display List Commands8-byte GBI (G_VTX 0x04, G_TRI1 0xBF, G_MTX 0x01, etc.).

Fixed-function rasterizer @ 62.5 MHz. Receives 64-bit commands from RSP.

Complete 64-bit Command Table (opcode bits 63:56 or 61:56)

0x08–0x0F

Triangle variants (edge coeffs s14.11, variable length)

0x24

Texture Rectangle

0x26–0x29

Load/Pipe/Tile/Full Sync (25/50/25/0 GCLK stalls)

0x2F

Set Other Modes (cycle_type, AA, Z, blend)

0x3C

Set Combine Mode ((A−B)×C+D)

0x34/0x35/0xF5

Load/Set Tile

0xF7–0xFF

Set Fill/Fog/Blend/Prim/Env/Color Image/Z Image

Color CombinerIndependent RGB/Alpha. Full mux table (0–7 inputs + extended C). Equation: ((A−B)×C + D) & 0x1FF. Blender: P×A + M×B with coverage AA. Cycle Modes & Stall Table (full table in Iter 11). TMEM: 4 KB (256×64-bit). Texture formats: RGBA32/16, CI8/4, IA16/8/4, I8/4, YUV16.

Host GPU Shader Mapping (GLSL/Vulkan)

vec4 combiner(vec4 A, vec4 B, vec4 C, vec4 D) { return clamp((A - B) * C + D, 0.0, 1.0); } Cycle-2 feedback as COMBINED. Static 0x3C analysis selects optimized shader at compile time.

RSP microcode software mixing (16–32 channels). AI DMA Timing: Interrupt fires on DMA start. Cleared by any write to AI_STATUS. Double-buffer bug workaround: if end at 0x2000 page boundary, next DRAM_ADDR += 0x2000. Full ABI command table + pseudocode (Iter 4).

4 MB RDRAM (expandable to 8 MB). Unified bus @ 250 MHz (9-bit internal). Random access latency 640 ns (~40 RCP cycles). Sequential burst 500 MB/s theoretical. UMA contention modeled with priority tree (VI > RDP-XBus > AI > PI > SI > SP > CPU) + token-bucket pseudocode (Iter 6–10).

RI Init in IPL3 (12-step broadcast + Expansion Pak detection, full sequence in Iter 9–10).

0x00000000–0x007FFFFF

RDRAM (4/8 MB)

0x04000000–0x04001FFF

RSP IMEM/DMEM

0x04040000–0x040FFFFF

RSP registers

0x04100000–0x041FFFFF

RDP registers

0x04300000–0x043FFFFF

MI (interrupts)

0x04400000–0x044FFFFF

VI

0x04500000–0x045FFFFF

AI

0x04600000–0x046FFFFF

PI (full bitfields)

0x04700000–0x047FFFFF

RI

0x04800000–0x048FFFFF

SI

0x10000000–0x1FBFFFFF

Cartridge ROM

0x1FC00000–0x1FC007BF

PIF boot ROM

Analog stick (±80 raw, calibrated), D-pad, A/B/C-buttons, L/R/Z/Start. PIF/Joybus Protocol: 64-byte packets. Controller Pak 32 KB SRAM via 0x02/0x03 commands + CRC5/CRC8. EEPROM (SI 0x04/0x05), SRAM/Flash (PI DMA Domain 2). Flash erase/program sequences + timings (85–300 ms sector, Iter 9).

Controller Pak (Joybus), EEPROM (SI), SRAM/Flash (PI). Full command sequences and CRC handling.

PIF ROM → CIC validation → IPL1 (52 instr) → IPL2 (IMEM) → IPL3 (DMEM). ROM Header (0x00–0x3F): PI settings, clockrate, entry PC, IPL3 checksum. CIC Variants (full table + checksum pseudocode in Iter 8). Expansion Pak probe via second-pass RI broadcast + 0x80000318 read.

Biggest Challenges & Solutions

Save/Boot/PI/SIStatic command replayers (host file I/O + simulated delays). Expansion Pak: Dynamic host RAM resize + RI_ERROR simulation.

REFORGE Validation Suite (automated CI)